The present invention relates to complementary metal oxide semiconductor (CMOS) device manufacturing, and more particularly to a method of fabricating CMOS devices having raised source/drain regions, without increased silicon growth on the gate electrode material.
As CMOS devices get smaller and smaller, the device performance can suffer from increased resistance of the contacts due to there smaller size, shallower junctions and scaled silicide thickness. As electrical junctions scale in depth, the depth of the metal silicide contact is often scaled such that the metallic silicide, which is formed, does not go too deep and xe2x80x98spikexe2x80x99 through or short the contact to the drain or source to the body of the device. This decreased thickness of metal silicide, however, increases the total resistance of the contact, which, in turn, can cause the performance of the device to suffer. This is true of all CMOS devices, but in particular to silicon-on-insulator (SOI) CMOS devices which have a thinner silicon region and which need to keep the contact resistance low.
To counter this effect, it has been suggested in the literature that silicon epitaxy be grown on the source and drain regions of the transistor. This additional epitaxial silicon layer can act as a sacrificial silicon layer; that is to say, it can be consumed during a subsequent reaction of the metal with the silicon during silicide formation at elevated temperatures. While this process of selective epitaxy, which grows on all exposed silicon surfaces, has been discussed in the literature for years, prior art processes also cause simultaneous growth of silicon on the polysilicon gate. While the growth of silicon on the source and drain regions is desirable, the growth of silicon on the gate electrode, i.e., polysilicon gate, is less desirable.
Growth of silicon on the gate electrode has several drawbacks. First, silicon grown on the gate electrode forms an overgrowth region over the edges of the sidewalls of the gate forming a mushroom shaped silicon ledge at the top of the gate. This growth was shown to cause dopant in the gate to diffuse into the newly grown silicon and cause a decrease in gate activation, or an increase in the gate inversion. This leads to device performance degradation. Finally, the increased growth on the gate makes it possible to form a link of conductive silicon from the gate over the spacer to the source/drain regions causing a short circuit. This is a known yield impact from selective epi.
In view of the above mentioned drawbacks with prior art selective epi processes, there is a continued need for developing a method which is capable of selectively forming epi silicon on the source/drain regions, while causing no substantial growth of epi silicon on any of the gate electrodes.
To solve the above problems, the prior art suggests forming a chemical vapor deposited (CVD) oxide or nitride on the top of the gate, prior to growth of the selective epi silicon layer. Such a prior art structure is shown, for example, in FIG. 1. Specifically, the structure shown in FIG. 1 comprises semiconductor substrate 10, patterned gate dielectric 14 formed on a surface of substrate 10, patterned polysilicon 16 formed on a portion of patterned gate dielectric 14, CVD oxide or nitride layer 18 formed atop the patterned polysilicon layer, and sidewall spacers 20 formed on vertical sidewalls of the patterned polysilicon layer and over a portion of the patterned gate dielectric.
While this prior art method does succeed in prevention of epi silicon growth on the gate, the prior art method suffers from the following drawbacks: First, is that fact that one must etch through this deposited film during the reactive-ion etching of the gate polysilicon electrode, which may effect the gate profile. Second, after the selective epi silicon layer is grown, a strip or removal of the deposited film on the gate is required. This may require a rather long wet etch since a plasma etch would also etch some of the source/drain regions. Moreover, if the film atop the gate is nitride, then a nitride wet etch could also attack the vertical gate sidewall or other exposed nitride sidewalls, or the wet may undercut the gate oxide which is present beneath the gate polysilicon, leading to defects in the device.
In view of the drawbacks associated with prior art methods, it is still desirable to provide a method which can inhibit the formation of silicon growth on the gate electrode through surface modification, while requiring only a reduced clean to allow further processing.
One object of the present invention is to provide a method of reducing the contact resistance in a CMOS device that is formed on a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate.
Another object of the present invention is to provide a method of forming a CMOS device having raised source/drain regions and without increased silicon growth on the gate electrode.
A yet further object of the present invention is to provide a method of inhibiting the formation of silicon growth on the gate electrode through surface modification, while requiring only a reduced clean to allow further processing.
An even further object of the present invention is to provide a method of forming a CMOS device which includes a step of forming a film on the gate electrode prior to epi silicon growth, wherein the film substantially inhibits the epi silicon growth on the gate without affecting the source/drain regions.
A still further object of the present invention is to provide a method of forming a CMOS device which includes a step of modifying at least the top horizontal surface of the gate polysilicon prior to epi growth, wherein the modified surface of the gate polysilicon substantially inhibits the epi silicon growth without affecting the source/drain regions.
These and other objects and advantages are achieved in the present invention by forming a nitrided surface layer atop the polysilicon gate electrode which inhibits the epitaxial growth of silicon on the polysilicon gate electrode. The nitrided surface layer is formed in the present invention by either implanting nitrogen-containing ions into the polysilicon gate electrode or by using a plasma nitridation process that incorporates nitrogen into the polysilicon gate electrode. Both of the above-mentioned techniques modify the top surface of the polysilicon gate electrode in such a manner that inhibits the growth of epitaxial silicon thereon.
Specifically, the method of the present invention comprises the steps of:
(a) forming a polysilicon layer atop a gate dielectric layer, said gate dielectric layer is formed on a surface of a semiconductor substrate;
(b) forming a nitrided surface layer on said polysilicon layer;
(c) selectively removing portions of said nitrided surface layer and said polysilicon layer stopping on said gate dielectric layer, while leaving a patterned stack of said nitrided surface layer and said polysilicon layer on said gate dielectric layer;
(d) forming sidewall spacers on at least exposed vertical sidewalls of said polysilicon layer not removed in step (c) as well as a portion of said gate dielectric layer;
(e) removing portions of said gate dielectric layer not protected by said sidewall spacers; and
(f) growing an epi silicon layer on exposed horizontal surfaces of said semiconductor substrate, wherein said epi silicon layer is inhibited from growing on said polysilicon layer of said patterned stack due to the presence of said nitrided surface layer.
The present invention also includes the step of: (g) removing the nitrided surface layer from said polysilicon layer.
In one embodiment of the present invention, the nitrided surface layer is formed utilizing a nitrogen ion implantation process. In another embodiment of the present invention, the nitrided surface layer is formed utilizing a plasma nitridation process.